Development of electronics technology has led to wide use of phase generators, in particular, phase generators including Delay Locked Loop (DLL) circuits and Phase Locked Loop (PLL) circuits. In general, DLL circuits allow generation of a certain number of output signals out of phase with respect to an input clock signal while PLL circuits allow generation of output signals whose phase has a fixed relation with the phase of a reference signal or clock signal.
FIG. 1 shows a typical architecture of a phase generator 1 comprising a DLL circuit. The DLL circuit may comprise a delay block Voltage Controlled Delay Line (VCDL), which in turn may comprise a chain of delay units being variable and adjustable in voltage, interposed between the input terminal and the output terminal of the delay block VCDL.
The delay units may be arranged in cascade with each other with the respective output terminals connected to the input terminals of the successive delay units. The delay block VCDL may receive at the input terminal the external clock signal CLKA and may generate at the output terminal a delayed clock signal CLKB, which is a copy of the external clock signal CLKA, delayed by the delay units exactly by a clock cycle. The DLL circuit also may comprise a control loop for feedback regulating the delay block VCDL using the delayed clock signal CLKB.
The control loop may comprise a Phase Detector PD that detects the phase delay between the external clock signal CLKA and the delayed clock signal CLKB and provides an impulse signal proportional to the phase difference detected. In particular, it may provide a first output signal UP if the external clock signal CLKA is in advance with respect to the delayed clock signal CLKB and a second output signal DOWN in the opposite case.
The control loop also may comprise a converter CP (Charge Pump) that allows conversion of the phase difference detected by the phase detector block PD into a current difference which, integrated on a capacity, generates a control signal Vc that feedback controls the delay units of the delay block VCDL. The phase generator 1 also may comprise a multiplexer MUX0 connected to the delay block VCDL of the circuit DLL. The multiplexer MUX0 may be driven by a select signal mux_sel_ch_0 so as to select one between the output signals of the delay units. Each signal at the output of the delay units of the delay block VCDL may be delayed with respect to the respective input signal by a fraction equal to 1/N of the period of the external clock signal CLKA, where N is the total number of the delay units in the delay block VCDL.
In consequence, by selecting through the signal mux_sel_ch_0 the n-th delay unit of the delay block VCDL, an output signal OUT0 of the multiplexer MUX0 comes comprises a delayed signal with respect to the external clock signal CLKA by a value equal to n/N of the period of the external clock signal CLKA. The phase generator 1 may also comprise a second multiplexer MUX1 connected to the delay block VCDL of the circuit DLL, substantially identical to the first multiplexer MUX0, which, driven by a second select signal mux_sel_ch_1, selects one among the output signals of the delay units for bringing back to its own output terminal an output signal OUT1 that is a delayed signal with respect to the external clock signal CLKA by a value equal to n/N of the period of the external clock CLKA (where n stands for the number of the delay units selected through the signal mux_sel_ch_1 and N stands for the number of the delay units in the block VCDL).
With the introduction of the second multiplexer, it may be possible to bring back to the output signals with delays different with respect to the external clock signal CLKA, so as to meet specific needs of the applications. A phase generator realized with the PLL circuit may have an oscillator controlled in voltage and a control loop which feedback regulates the oscillator by using the output signal of the oscillator compared with the external clock signal. The oscillator may be realized with a chain of delay units loop-locked connected in a similar way as the delay block VCDL above described.
The phase generators realized with circuits DLL or PLL may have to be suitably controlled or tested for verifying the good operation of the same. The typical tests may provide to verify:
1. malfunctions of the delay units;
2. malfunctions of the multiplexers MUX;
3. that there is a “monotonous” behavior among the select signals at the input and the respective phase shift of the signals output from each multiplexer with respect to the external clock signal CLKA; and
4. a linearity in the delay of the output signal OUT of the signal generator with respect to the external clock signal CLKA.
For each type of test indicated, a series of rather elaborate measures may be necessary, which use the accurate and precise machines or instruments able to measure very short times, of the order of the switch of one of the delay units of the chain, thus substantially of the order of the picoseconds. These apparatuses may be expensive.
Moreover, the times requested for carrying out the predefined measures may be particularly long and rather burdensome. For example, in the case of the test for malfunction of the delay units, it may be necessary to measure the output signal of each delay unit of the chain and to compare this measure with the measure of the output signal of the successive delay units, as well as to compare all their combinations. According to the application, these types of testing can be all or in part carried out, but in any case, although advantageous under several aspects, such approaches may be long and expensive.